Embodiments relate to a semiconductor device and a method for fabricating the same, and more particularly, to a technology for preventing migration of a metallic material in a through silicon via (TSV) when forming the TSV.
Among packaging technologies of semiconductor integrated circuits (ICs), a three-dimensional (3D) stack technology has been rapidly developed to increase packaging density and reduce the size of electronic components, resulting in production of high-performance semiconductor devices. A 3D stacked package is formed by stacking a plurality of chips that have the same memory capacity, and is generally called a chip stack package.
A chip stack package can be mass produced at a reduced cost. However, in a stack chip package, as the number and size of stacked chips increase, a line space for electrical connection of the stacked chips may be reduced to an insufficient size.
A conventional stack chip package includes a plurality of chips mounted on substrates which are attached to each other. This configuration enables a bonding pad of each chip to be electrically coupled to a conductive circuit pattern formed in or over a substrate through wiring. However, since a space for wire bonding and a circuit pattern area for the substrate connected to the wire are needed, the size of the stack chip package increases.
In order to solve the above-mentioned problems, a TSV structure has been proposed. After forming a TSV in each chip in a wafer, physical and electrical connection between chips is vertically implemented by the TSV.
However, if the TSV is repetitively exposed to heat treatment during a fabrication process, then a metallic material (e.g., Cu ion) contained in the TSV may be stressed and gather in an active region of the semiconductor device. The accumulated metallic material may serve as a generation and recombination center of minority carriers, and thus a leakage current may occur. As a result, electrical characteristics of a package of semiconductor devices are deteriorated.
In addition, when forming a TSV configured to pass through a semiconductor substrate and an interlayer insulation film, Cu ions may migrate through oxide films before being absorbed in an active region of the semiconductor substrate of the cell region, thus causing a crack in a bit line contact deposited over the active region.